In order to build faster and more complex integrated circuits, semiconductor manufacturers have increased the number of components in the integrated circuit, while reducing the overall size of the circuit. The small circuit dimensions require multiple metal interconnect layers to electrically couple the vast number of components within the integrated circuit. As successive layers of metal and dielectric materials are deposited, the surface topography can become uneven. To be manufactured reliably, metal interconnect patterns must be defined on a smooth, planar surface. Some type of planarization process is necessary to even out the surface during the formation of multiple layers of metal interconnects.
A planarization process is typically performed after the deposition of a dielectric passivation layer to reduce the topographic contrast of the passivation layer. A conductive metal layer is then deposited on the smooth surface, and an interconnect pattern is defined thereon. A planar surface can be formed during device fabrication by a variety of methods. In one technique, a deposition and etchback process can be used in which a planarization layer is deposited over the surface to be planarized, followed by a non-selective plasma etching process. The plasma etching process removes both the planarization material and the underlying dielectric material at approximately the same rate.
Additionally, polishing planarization processes have been developed which abrasively remove material from the surface of the substrate. The polishing process is known in the art as chemical-mechanical-polishing (CMP). In the CMP process, the surface to be planarized is brought into contact with a rotating polishing pad in the presence of an abrasive slurry. A portion of the surface layer is then abrasively removed by the mechanical action of the polish pad and the chemical action of the slurry.
Although both the etchback process and the CMP process are effective in forming a planar surface, both planarization processes leave a particulate residue containing metal contaminants on the substrate surface. In the etchback process, particulate matter and metal contaminants originate from either the planarization material or from metal contaminants introduced during the etching process. The particulate matter can include metals originating from a planarization material, such as photoresist or a spin-on-glass planarization layer. Correspondingly, metal contaminants in the CMP process originate from the chemical constituents of the polishing slurry. The metal contaminants introduced by the planarization process include alkaline metals, such as sodium, potassium, and the like, and iron.
The metal contaminants are typically removed from the substrate surface using a caustic solution containing ammonium hydroxide or ammonium hydroxide mixed with hydrogen peroxide. Additionally, particulate matter has been removed by brush scrubbing with deionized water and ammonium hydroxide. While these processes are effective at removing metal and particulate contaminants, the chemical constituents of the caustic solutions can diffuse through defects in a dielectric layer overlying a metal interconnect. The caustic chemicals are highly reactive with metals, such as aluminum, aluminum alloys, refractory metals, and the like. Once the caustic chemicals reach the surface of an aluminum interconnect, a rapid chemical reaction takes place between the caustic chemicals and the metal interconnect, which in severe cases can result in void formation in a pattern metal interconnect. The formation of voids in a metal interconnect can cause catastrophic device failure. In severe cases, large regions of the metal interconnect can be completely removed by the caustic solution. Accordingly, an improved contaminant cleaning process is necessary to fabricate high reliability semiconductor devices.